MAX4533CPP 查看數據表（PDF） - Maxim Integrated

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MAX4533CPP

Quad, Rail-to-Rail, Fault-Protected, SPDT Analog Switch

Maxim Integrated 

Quad, Rail-to-Rail, Fault-Protected,

SPDT Analog Switch

Test Circuits/Timing Diagrams (continued)

LOGIC +3V

INPUT

50%

0V

VCOM

VO1

0.9VO

SWITCH 0V

OUTPUT VCOM

VO2

SWITCH 0V

OUTPUT

tD

tD

Figure 3. Break-Before-Make

VIN_

IN_

50Ω

V+

V+

VCOM_

MAX4533

0.9VO

+15V

MAX4533

LOGIC

INPUT

V+

NO

VCOM COM_

NC

IN_

GND

V-

VO2 RL1

RL2

CL2

VO1

CL1

-15V

RL = 1000Ω

CL = 35pF

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

LOGIC 0 INPUT.

V+

VIN_

0V

NC_ OR NO_

GND V-

V-

VOUT

CL

100pF

V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.

Figure 4. Charge Injection

VOUT

∆ VOUT

∆ VOUT IS THE MEASURED VOLTAGE DUE TO CHARGE-

TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF.

Q = ∆ VOUT x CL

ADDRESS SELECT

V+

V+

V+

NO_

MAX4533 NC_

IN_

COM_

GND V-

1MHz

CAPACITANCE

ANALYZER

V-

V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.

Figure 5. COM_, NO_, NC_ Capacitance

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