LH28F160S5D-L90 查看數據表（PDF） - Sharp Electronics

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LH28F160S5D-L90

16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)

Sharp Electronics 

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory

arrays. SHARP provides three control inputs to

accommodate multiple memory connections. Three-

line control provides for :

a. Lowest possible memory power consumption.

b. Complete assurance that data bus contention

will not occur.

To use these control inputs efficiently, an address

decoder should enable CE# while OE# should be

connected to all memory devices and the system’s

READ# control line. This assures that only selected

memory devices have active outputs while

deselected memory devices are in standby mode.

RP# should be connected to the system

POWERGOOD signal to prevent unintended writes

during system power transitions. POWERGOOD

should also toggle during system reset.

5.2 STS and Block Erase, Full Chip

Erase, (Multi) Word/Byte Write and

Block Lock-Bit Configuration Polling

STS is an open drain output that should be

connected to VCC by a pullup resistor to provide a

hardware method of detecting block erase, full chip

erase, (multi) word/byte write and block lock-bit

configuration completion. In default mode, it

transitions low after block erase, full chip erase,

(multi) word/byte write or block lock-bit configuration

commands and returns to VOH when the WSM has

finished executing the internal algorithm. For

alternate STS pin configurations, see the Configu-

ration command (Table 3 and Section 4.14).

STS can be connected to an interrupt input of the

system CPU or controller. It is active at all times.

STS, in default mode, is also High Z when the

device is in block erase suspend (with (multi)

word/byte write inactive), (multi) word/byte write

suspend or deep power-down modes.

LH28F160S5-L/S5H-L

5.3 Power Supply Decoupling

Flash memory power switching characteristics

require careful device decoupling. System

designers are interested in three supply current

issues; standby current levels, active current levels

and transient peaks produced by falling and rising

edges of CE# and OE#. Transient current

magnitudes depend on the device outputs’

capacitive and inductive loading. Two-line control

and proper decoupling capacitor selection will

suppress transient voltage peaks. Each device

should have a 0.1 µF ceramic capacitor connected

between its VCC and GND and between its VPP

and GND. These high-frequency, low inductance

capacitors should be placed as close as possible to

package leads. Additionally, for every eight devices,

a 4.7 µF electrolytic capacitor should be placed at

the array’s power supply connection between VCC

and GND. The bulk capacitor will overcome voltage

slumps caused by PC board trace inductance.

5.4 VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target

system requires that the printed circuit board

designers pay attention to the VPP power supply

trace. The VPP pin supplies the memory cell current

for block erase, full chip erase, (multi) word/byte

write and block lock-bit configuration. Use similar

trace widths and layout considerations given to the

VCC power bus. Adequate VPP supply traces and

decoupling will decrease VPP voltage spikes and

overshoots.

5.5 VCC, VPP, RP# Transitions

Block erase, full chip erase, (multi) word/byte write

and block lock-bit configuration are not guaranteed

if VPP falls outside of a valid VPPH1 range, VCC falls

outside of a valid VCC1/2 range, or RP# = VIL. If

VPP error is detected, status register bit SR.3 is set

to "1" along with SR.4 or SR.5, depending on the

attempted operation. If RP# transitions to VIL during

block erase, full chip erase, (multi) word/byte write

or block lock-bit configuration, STS (if set to

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