GL800USB 查看數據表（PDF） - Genesys Logic

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GL800USB

3.3 V, USB 2.0 UTMI compliant transceiver

Genesys Logic 

GL800USB - USB2.0 UTMI COMPLIANT TRANSCEIVER

6. Functional Description

6.1 Transmit Operation

6.1.1 Transmit State Diagram

HRST#

Reset

!TXRDY

!HRST#

!TXVLD

TX Wait

TXVLD

TX Hold

Reg Empty

EOP not

done

Send SYNC

TX Hold

Reg Full

TX Data Load !TXVLD

TXRDY

TX Hold

Reg Empty

Send EOP

!TXRDY

TX Data Wait

!TXRDY

TX Hold

Reg Full

Transmit must be asserted to enable any transmissions.

The SIE asserts TXVLD to begin a transmission.

The SIE negates TXVLD to end a transmission.

After the SIE asserts TXVLD it can assume that the transmission has started when it

detects TXRDY asserted.

The SIE assumes that the UTM has consumed a data byte if TXRDY and TXVLD are

asserted.

The SIE must have valid packet information (PID) asserted on the Data bus

coincident with the assertion of TXVLD. Depending on the UTM implementation,

TXRDY may be asserted by the Transmit State Machine as soon as one CLK after

the assertion of TXVLD.

TXVLD and TXRDY are sampled on the rising edge of CLKOUT.

The Transmit State Machine does not automatically generate Packet ID’s (PIDs) or

©2000-2001 Genesys Logic Inc.—All rights reserved.

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