ICS581G-02IT 查看數據表（PDF） - Integrated Circuit Systems
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ICS581G-02IT Datasheet PDF : 9 Pages
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ICS581-01/02
Zero Delay Glitch-Free Clock Multiplexer
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 (-01)
16 (-02)
Pin
Name
S0
S1
VDD
INA
INB
GND
FBIN
OE0
OE1
GND
CLK4
CLK3
CLK2
CLK1
VDD
SELA
DIV
Pin
Type
Input
Input
Power
Input
Input
Power
Input
Input
Input
Power
Output
Output
Output
Output
Power
Input
Input
Pin Description
Select 0 for frequency range. See table. Internal pull-up.
Select 1 for frequency range. See table. Internal pull-up.
Power Supply. Connect to +3.3 V or +5 V.
Input Clock A.
Input Clock B.
Connect to ground.
Feedback input. Connect to a clock output.
Output enable 0. See table. Internal pull-up.
Output enable 1. See table. Internal pull-up.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Power Supply. Connect to +3.3 V or +5 V.
Mux select. Selects INA when high. Internal pull-up.
Timeout select. See table. Internal pull-up.
Device Operation
The ICS581-01 and ICS581-02 are very similar.
Following is a description of the operation of the
ICS581-01 and the differences of the ICS581-02.
The ICS581-01 is a PLL-based, zero delay, clock
multiplexer. The device consists of an input multiplexer
controlled by SELA that selects between two clock
inputs. The output of the mux drives the reference input
of a phase locked loop. The other input to the PLL
comes from a feedback input pin called FBIN. The
output of the PLL drives four low skew outputs. These
chip outputs are therefore buffered versions of the
selected input clock with zero delay and 50/50 duty
cycle.
For correct operation, one of the clock outputs must be
connected to FBIN. In this datasheet, CLK4 is shown
as the feedback, but any one of the four clock outputs
can be used. If output termination resistors are used,
the feedback should be connected after the resistor. It
is a property of the PLL used on this chip that it will
align rising edges on FBIN and either INA or INB
(depending on SELA). Since FBIN is connected to a
clock output, this means that the outputs appear to
align with the input with zero delay.
When the input select (SELA) is changed, the output
clock will change frequency and/or phase until it lines
up with the new input clock. This occurs in a smooth,
gradual manner without any short pulses or glitches
and will typically take a few tens of microseconds.
The part must be configured to operate in the correct
frequency range. The table on page two gives the
recommended range.
The four low skew outputs are controlled by two output
enable pins that allow either one, three, or four
simultaneous outputs. If both OE pins are low, the PLL
is powered down.
MDS 581-01/02 F
3
Revision 071504
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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