OPERATION
LTC2601/LTC2611/LTC2621
VREF = VCC
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
OUTPUT
VOLTAGE
0
32, 768
65, 535
INPUT CODE
(a)
INPUT CODE
(c)
Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
OUTPUT
VOLTAGE
2601 F03
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
R = 0.115
TYP
6
0.38 ± 0.10
10
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PIN 1
PACKAGE TOP MARK
OUTLINE (SEE NOTE 6)
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3.00 ±0.10 1.65 ± 0.10
(4 SIDES) (2 SIDES)
0.75 ±0.05
0.00 – 0.05
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2601fb
15