UR5HCSPI-FB 查看數據表（PDF） - Semtech Corporation
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UR5HCSPI-FB Datasheet PDF : 20 Pages
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SPI COMMUNICATION CHANNEL
SPI data transfers can be performed at a maximum clock rate of 500 KHz. When the UR5HCSPI asserts the _ATN
signal to the host Master, the data will have already been loaded into the data register waiting for the clocks from
the master. The Slave Select (SS) line can be tied permanently to Ground if the UR5HCSPI is the only slave device
in the SPI network. One _ATN signal is used per each byte transfer. If the host fails to provide clock signals for
successive bytes in the data packet within 120 mS, the transmission will be aborted and a new session will be
initiated by asserting a new ATN signal. In this case, the whole packet will be re-transmitted.
If the SPI transmission fails 20 times consecutively, the synchronization between the master and slave may be lost.
In this case, the UR5HCSPI will enter the reset state.
The UR5HCSPI implements the SPI communication protocol according to the following diagram:
CPOL = 0 ---------- SCK line idles in low state
CPHA = 1 ---------- SS line is an output enable control
_ATN SIGNAL
SCK (CPOL=0)
_SS
SAMPLE INPUT
DATA OUTPUT
(CPHA=1)
?
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 4: SPI Communication Protocol
When the host sends commands to the keyboard, the UR5HCSPI requires that the minimum and maximum
intervals between two successive bytes be 200 µS and 5 mS respectively.
Figure 5: Transmitting Data Waveforms:
Figure 6: Receiving Data Waveforms
Copyright Semtech 1997-2001
9
DOC5-SPI-DS-117
www.semtech.com
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