CS62180A-IP 查看數據表（PDF） - Cirrus Logic

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CS62180A-IP

T1 Framer

Cirrus Logic 

CS62180A

CS62180B

Frame

X 11 12 13 14 15 16 17 18 19 20 21 22 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Data Link

C1 C2 C3 C4 C5 C6 M3 A1 A2 S1 S2 S3 S4

RMSYNC

72 1 2 3

RFSYNC

RSIGSEL

RSIGFR

B

A

B

A

B

RLCLK

RLINK

FS C1 C2 C3 C4 C5 C6 M3 A1 A2 S1 S2 S3 S4 FS FS

Figure 17. SLC-96® Multiframe Receive Timing

Frame 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9

RFSYNC

RMSYNC

RLINK

RSIGSEL

RSIGFR

RLCLK

193E Timing

Figure 18. T1DM Multiframe Receive Timing

SLC-96® Timing

Link data can be identified by RLCLK, which

goes high for all odd numbered frames. RSIGFR

is high for signaling frames, and low at all other

times. RSIGSEL runs at twice the frequency of

RMSYNC. Logical combination of RMSYNC

and RSIGSEL provides a way to distinguish the

6th, 12th, 18th, and 24th frames for external mul-

tiplexing of signaling channels. RMSYNC is

high for frames containing A and B signaling

bits, and RSIGSEL is high for frames with A

and C bits. Refer to Figure 16 for a timing dia-

gram.

The CS62180B will output 36 bits of the DL on

RLINK using RLCLK. RSIGSEL can be used to

locate the DL bits. RSIGSEL will be held high

in those frames where Fs bits and the last spoiler

bit are present (frames 58 to 11). RSIGSEL is

held low in all other frames (frames 12 to 57).

RSIGFR is high for signaling frames, and low at

all other times. RMSYNC is high for frames

containing A signaling bits, and low for frames

containg B bits. Refer to Figure 17 for a timing

diagram. In SLC-96® mode, the start of a new

multiframe occurs on the second rising edge of

RMSYNC which occurs while RSIGSEL is high.

A multiframe synchronization signal can be gen-

erated from RMSYNC and RSIGSEL using the

24

DS225PP1

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