STPCE1EDBI 查看數據表（PDF） - STMicroelectronics

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STPCE1EDBI

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

DESIGN GUIDELINES

6.4. PLACE AND ROUTE

RECOMMENDATIONS

6.4.1. GENERAL RECOMMENDATIONS

All clock signals have to be routed first and

shielded for speeds of 27MHz or higher. The high

speed signals follow the same constraints, as for

the memory and PCI control signals.

Some STPC Interfaces run at high speed and

need to be carefully routed or even shielded like:

The next interfaces to be routed are Memory and

PCI.

1) Memory Interface

2) PCI bus

3) 14 MHz oscillator stage

All the analog noise-sensitive signals have to be

routed in a separate area and hence can be

routed indepedently.

Figure 6-15. Shielding signals

ground ring

shielded signal line

ground pad

ground pad

shielded signal lines

Release 1.3 - January 29, 2002

71/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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