STPCI2GDYI(2002) 查看數據表（PDF） - STMicroelectronics

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STPCI2GDYI
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

ELECTRICAL SPECIFICATIONS

Figure 4-2. CLK Timing Measurement Points

T1

T2

VIH (MIN)

VRef

CLK VIL (MAX)

T5

T3

T4

LEGEND:

T1 - One Clock Cycle

T2 - Minimum Time at VIH

T3 - Minimum Time at VIL

T4 - Clock Fall Time

T5 - Clock Rise Time

NOTE; All sIgnals are sampled on the rising edge of the CLK.

Issue 1.0 - July 24, 2002

47/111

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