PDM31548SA20TY 查看數據表（PDF） - Paradigm Technology

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PDM31548SA20TY

128K x 16 CMOS 3.3V Static RAM

Paradigm Technology 

PRELIMINARY

Write Cycle 1 Timing Diagram(5) (WE Controlled)

tWC

ADDRESSES

tAW

tAS

tWP

tAH

WE

tCW

CE

tBW

UB, LB

DOUT

tHZWE(6)

(3)

High Impedance

tDS

tLZWE(6)

(4)

tDH

DIN

Data Stable

Write Cycle 2 Timing Diagram(5) (CE Controlled)

tWC

ADDRESSES

tAS

tAW

tWP

WE

tCW

CE

tBW

UB, LB

DOUT

tLZBE(6)

tLZCE(6)

tHZWE(6)

tAH

High Impedance

tDS

tDH

DIN

Data Stable

PDM31548

1

2

3

4

5

6

7

8

9

10

11

12

Rev. 1.3 - 4/13/98

7

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