QL3012-0PL84I(1999) 查看數據表（PDF） - QuickLogic Corporation
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产品描述 (功能)
生产厂家
QL3012-0PL84I
(Rev.:1999)
(Rev.:1999)
QuickLogic Corporation
QL3012-0PL84I Datasheet PDF : 10 Pages
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QL3012
Clock Cells
Symbol
Parameter
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Propagation Delays (ns)
Loads per Half Column [7]
1 2 3 4 8 10 11
1.2 1.2 1.3 1.3 1.5 1.6 1.7
0.7 0.7 0.7 0.7 0.7 0.7 0.7
0.8 0.8 0.9 0.9 1.1 1.2 1.3
I/O Cells
Symbol
Parameter
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up
Time
Input Register Clock Enable Hold Time
Propagation Delays (ns)
Fanout [5]
1
2
3
4
8
10
1.3 1.6 1.8 2.1 3.1 3.6
3.1 3.1 3.1 3.1 3.1 3.1
0.0 0.0 0.0 0.0 0.0 0.0
0.7 1.0 1.2 1.5 2.5 3.0
0.6 0.9 1.1 1.4 2.4 2.9
2.3 2.3 2.3 2.3 2.3 2.3
0.0 0.0 0.0 0.0 0.0 0.0
Symbol
Parameter
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [8]
Output Delay Low to Tri-State [8]
Propagation Delays (ns)
Output Load Capacitance (pF)
30
50
75
100 150
2.1
2.5
3.1
3.6 4.7
2.2
2.6
3.2
3.7 4.8
1.2
1.7
2.2
2.8 3.9
1.6
2.0
2.6
3.1 4.2
2.0
1.2
Notes:
[7] The array distributed networks consist of 40 half columns and the global distributed networks consist of
44 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11
loads per half column.
[8] The following loads are used for tPXZ:
1KΩ
tPHZ
5 pF
1KΩ
tPLZ
5 pF
4-32
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