CS1880-IB 查看數據表（PDF） - Cirrus Logic

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CS1880-IB

Octal E1 Line Interface Unit

Cirrus Logic 

CS61880

14.14 LOS/AIS Mode Enable Register (0Dh)

BIT NAME

Description

[7:0] LAME 7-0 Setting bit n to “1” enables ETSI 300 233 compliant LOS/AIS for channel n; setting bit n to “0”

enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to 00h after

power-up or reset.

14.15 Automatic TAOS Register (0Eh)

BIT NAME

Description

[7:0] ATAO 7-0 Setting bit n to “1” enables automatic TAOS generation on channel n when LOS is detected.

Register bits default to 00h after power-up or reset.

14.16 Global Control Register (0Fh)

BIT NAME

Description

This register is the global control for the AWG Auto-Increment, Automatic AIS insertion,

encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for

all eight channels. Register bits default to 00h after power-up or reset.

The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address

[7] AWG Auto- Register (17h) (See Section 14.24 on page 39) after each access. Thus, when this bit is set,

Increment the phase samples address portion of the address register increments after each read or

write access. This bit must be set before any bit in the AWG Enable register is set, if this

function is required.

On LOS, this bit controls the automatic AIS insertion into all eight receiver paths.

[6] RAISEN

0 = Disabled

1 = Enabled

[5]

RSVD

RESERVED (This bit must be set to 0.)

Line encoding/decoding Selection

[4] CODEN

0 = HDB3

1 = AMI

Jitter Attenuator FIFO length Selection

[3]

FIFO

0 = 32 bits

LENGTH

1 = 64 bits

Jitter Attenuator Corner Frequency Selection

0 = 1.25Hz

[2]

JACF

1 = 2.50Hz

These bits select the position of the Jitter Attenuator.

Table 11. Jitter Attenuator Position Selection

[1:0] JASEL [1:0]

JASEL 1

0

0

1

1

JASEL 0

0

1

0

1

POSITION

Disabled

Transmit Path

Disabled

Receive Path

DS450PP2

37

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