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74LV132A

  

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Texas-Instruments
Texas Instruments
74LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

Description
The LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.
The LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

Features
• 2-V to 5.5-V VCC Operation
• Max tpd of 9 ns at 5 V
• Typical VOLP (Output Ground Bounce) <0.8 V at
   VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2.3 V at
   VCC = 3.3 V, TA = 25°C
• Support Mixed-Mode Voltage Operation on All
   Ports
• Latch-Up Performance Exceeds 250 mA per
   JESD 17
• Ioff Supports Live Insertion, Partial Power-Down
   Mode, and Back Drive Protection
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 200-V Machine Model (A115-A)
   – 1000-V Charged-Device Model (C101)

Applications
• Industrial PC: Rugged PC and Laptop
• Access Control and Security: Camera
   Surveillance IP Network
• Vending, Payment and Change Machines
• Patient Monitoring STB / DVR / Streaming Media
   (Withdraw)
• Other Motor Drives (Such as Switch Reluctance)


other parts : LV132A  SN54LV132A  SN54LV132AFK  SN54LV132AJ  SN54LV132AW  SN74LV132A  SN74LV132AD  SN74LV132ADB  SN74LV132ADBR  SN74LV132ADG4  
74LV132A PDF
TI
Texas Instruments
74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

description/ordering information
The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.
The ’LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

● 2-V to 5.5-V VCC Operation
● Max tpd of 9 ns at 5 V
● Typical VOLP (Output Ground Bounce)
   <0.8 V at VCC = 3.3 V, TA = 25°C
● Typical VOHV (Output VOH Undershoot)
   >2.3 V at VCC = 3.3 V, TA = 25°C
● Support Mixed-Mode Voltage Operation on
   All Ports
● Latch-Up Performance Exceeds 250 mA Per
   JESD 17
● ESD Protection Exceeds JESD 22
   − 2000-V Human-Body Model (A114-A)
   − 200-V Machine Model (A115-A)
   − 1000-V Charged-Device Model (C101)



other parts : LV132A  SN54LV132A  SN74LV132A  SN74LV132AD  SN74LV132ADB  SN74LV132ADBR  SN74LV132ADBRE4  SN74LV132ADBRG4  SN74LV132ADE4  SN74LV132ADG4  
74LV132A PDF

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