Figure 43. Peripheral I/O WRITE Timing
ALE /AS
PSD834F2V
A/D BUS
ADDRESS
DATA OUT
tWLQV (PA)
tWHQZ (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI02898
) Table 51. Port A Peripheral Data Mode WRITE Timing
ct(s Symbol
Parameter
Conditions
-10
-15
-20
Unit
Min Max Min Max Min Max
du tWLQV–PA
WR to Data Propagation Delay
(Note 2)
42
45
55 ns
Pro tDVQV–PA
Data to Port A Data Propagation Delay
(Note 5)
38
40
45 ns
te tWHQZ–PA WR Invalid to Port A Tri-state
(Note 2)
33
33
35 ns
le Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
o 2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
s 3. Any input used to select Port A Data Peripheral mode.
b 4. Data is already stable on Port A.
Obsolete Product(s) - O 5. Data stable on ADIO pins to data on Port A.
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