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CS8403A-CS

96 kHz Digital Audio Transmitter

Cirrus Logic 

CS8403A CS8404A

CS8404A DESCRIPTION

The CS8404A accepts 16- to 24-bit audio samples

through a serial port configured in one of seven for-

mats, provides several pins dedicated to particular

channel status bits, and allows all channel status,

user, and validity bits to be serially input through

port pins. This data is multiplexed, the parity bit is

generated, and the bit stream is biphase-mark en-

coded and driven through an RS422 line driver.

The CS8404A operates as a professional or con-

sumer interface transmitter selectable by pin 2,

PRO. As a professional interface device, the dedi-

cated channel status input pins are defined accord-

ing to the professional standard, and the CRC code

(C.S. byte 23) can be internally generated.

As a consumer device, the dedicated channel status

input pins are defined according to the consumer

standard. A submode provided under the consumer

mode is compact disk, CD, mode. When transmit-

ting data from a compact disk, the CD subcode port

can accept CD subcode data, extract channel status

information from it, and transmit it as user data.

The master clock, MCK, controls timing for the en-

tire chip and must be 128x Fs. As an example, if

stereo data is input to the CS8404A at 44.1 kHz,

MCK input must be 128 times that or 5.6448 MHz.

Audio Serial Port

The audio serial port is used to enter audio data and

consist of three pins: SCK, SDATA, and FSYNC.

SCK clocks in SDATA, which is double buffered,

while FSYNC delineates the audio samples and

may indicate the particular channel, left or right. To

support many different interfaces, M2, M1, and M0

select one of seven different formats for the serial

port. The coding is shown in Table 3 while the for-

mats are shown in Figure 16. Format 0 and 1 are de-

signed to interface with Crystal ADCs. Format 2

communicates with Motorola and TI DSPs.

Format 3 is reserved. Format 4 is compatible with

the I2S standard. Formats 5 and 6 make the

CS8404A look similar to existing 16- and 18-bit

DACs, and interpolation filters. Format 7 is an

MSB-last format and is conducive to serial arith-

metic. SCK and FSYNC are outputs in Format 0

and inputs in all other formats. In Format 2, the ris-

ing edge of FSYNC delineates samples and the fall-

ing edge must occur a minimum of one bit period

before or after the rising edge. In all formats

except 2, FSYNC contains left/right information

requiring both edges of FSYNC to delineate sam-

ples. Formats 5 and 6 require a minimum of 16- or

18-bit audio words respectively. In all formats oth-

er than 5 and 6, the CS8404A can accept any word

length from 16 to 24 bits by adding leading zeros in

format 7 and trailing zeros in the other formats, or

by restricting the number of SCK periods between

active edges of FSYNC to the sample word length.

M2 M1 M0

Format

0 0 0 0 - FSYNC & SCK Output

0 0 1 1 - Left/Right, 16-24 Bits

0 1 0 2 - Word Sync, 16-24 Bits

0 1 1 3 - Reserved

1 0 0 4 - Left/Right, I2S Compatible

1 0 1 5 - LSB Justified, 16 Bits

1 1 0 6 - LSB Justified, 18 Bits

1 1 1 7 - MSB Last, 16-24 Bits

Table 3. CS8404A Audio Port Modes

FSYNC must be derived from MCK, either through

a DSP using the same clock, or using counters. If

FSYNC moves (jitters) with respect to MCK by

four MCK periods, the internal counters and CBL

may be reset. Appendix B contains more informa-

tion on the relationship between FSYNC and

MCK.

DS239PP1

19

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