CS492705-CL Просмотр технического описания (PDF) - Cirrus Logic

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CS492705-CL

Multi-Channel Digital Audio Decoders

Cirrus Logic 

CS4923/4/5/6/7/8/9

3.2 Termination Requirements

The CS4923/4/5/6/7/8/9 incorporates open drain

pins which must be pulled high for proper

operation. INTREQ (pin 20) is always an open

drain pin which requires a pull-up for proper

operation. When in the I2C serial communication

mode, the SCDIO signal (pin 19) is open drain and

thus requires a pull-up for proper operation.

Due to the internal, multiplexed design of the pins,

certain signals may or may not require termination

depending on the mode being used. If a parallel

host communication mode is not being used,

GPIO[11:0] must be terminated or driven as these

pins will come up as high impedance inputs and

will be prone to oscillation if they are left floating.

The specific termination requirements may vary

since the state of some of the GPIO pins will

determine the communication mode at the rising

edge of reset (please see section 6 for more

information). For the explicit termination

requirements of each communication mode please

see the typical connection diagrams.

Generally a 4.7k Ohm resistor is recommended for

open drain pins while a 10k Ohm resistor is

sufficient for the GPIO pins and unused inputs.

3.3 Phase Locked Loop Filter

The internal phase locked loop (PLL) of the

CS4923/4/5/6/7/8/9 requires an external filter for

successful operation. The topology of this filter and

component values are shown in the typical

connection diagrams. Care should be taken when

laying out the filter circuitry to minimize trace

lengths and to avoid any close routing of high

frequency signals. Any noise coupled on to the

filter circuit will be directly coupled into the PLL,

which could affect performance.

24

DS262F2

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