CS493115 데이터 시트보기 (PDF) - Cirrus Logic

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CS493115

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

11. HARDWARE CONFIGURATION

After download or soft reset, and before

kickstarting the application (please see the Audio

Manager in the Application Messaging Section of

any application code user’s guide for more

information on kickstarting), the host has the option

of changing the default hardware configuration.

Hardware configuration messages are used to

physically reconfigure the hardware of the audio

decoder, as in enabling or disabling address

checking for the serial communication port.

Hardware configuration messages are also used to

initialize the data type (i.e., PCM or compressed)

and format (e.g., I2S, Left Justified, Parallel, or

Serial Bursty) for digital data inputs, as well as the

data format and clocking options for the digital

output port.

In general, the hardware configuration can only be

changed immediately after download or after soft

reset. However, some applications provide the

capability to change the input ports without

affecting other hardware configurations after

sending a special Application Restart message

(please see the Audio Manager in any Application

Code User’s Guide to determine whether the

Application Restart message is supported).

Serial digital audio data bit placement and sample

alignment is fully configurable in the CS493XX

including left justified, right justified, delay bits or

no delay bits, variable sample word sizes, variable

output channel count, and programmable output

channel pin assignments and clock edge polarity to

integrate with most digital audio interfaces. If a

mode is needed which is not presented, please

consult your sales representative as to its

availability.

11.1. Address Checking

When using one of the serial communication

modes, I2C or SPI, as discussed in Section 6.1,

“Serial Communication” on page 36, it is necessary

to send a 7-bit address along with a read/write bit

at the start of any serial transaction. By default,

address checking is disabled in the CS493XX.

See below for how to enable address checking.

The following 4-word hex message configures the

address checking circuitry of the CS493XX: It

should be noted that this will allow the host to

enable address checking and change the address

of the device. If address checking disabled is

acceptable, then these messages do not need to

be sent.

0x800252

0x00FFFF

0x800152

0xHH0000

In the last word the following bits should replace

HH:

Bits 23:17 - New Address to use for checking (if

enabling address checking)

Bit 16 - 1 = Address checking on

0 = Address checking off

11.2. Input Data Hardware

Configuration

Both data format (I2S, Left Justified, Parallel, or

Serial Bursty) and data type (compressed or PCM)

are required to fully define the input port’s

hardware configuration. The DAI and the CDI are

configured by the same group of messages since

their configurations are interrelated. The naming

convention of the input hardware configuration is

as follows:

INPUT A B C D

where A, B, C and D are the parameters used to

fully define the input port. The parameters are

defined as follows:

A - Data Type

B - Data Format (This is a don’t care for parallel

modes of data delivery)

C - SCLK Polarity

D - FIFO Setup (only valid for parallel modes of

data delivery)

The following tables show the different values for

each parameter as well as the hex message that

needs to be sent. When creating the hardware

configuration message, only one hex message

should be sent per parameter. It should be noted

that the entire B parameter hex message must be

sent, even if one of the input ports has been

defined as unused by the A parameter.

74

DS339F7

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