CS4353 데이터 시트보기 (PDF) - Cirrus Logic

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CS4353

3.3 V Stereo Audio DAC with 2 VRMS Line Output

Cirrus Logic 

CS4353

Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-

neously with VCP.

When power is removed and the VCP voltage reaches a defined threshold, Voff, the POR circuit asserts the

internal reset low, resetting all of the digital circuitry.

4.7 Initialization

When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization

sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA.

The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high,

the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alterna-

tively, if no external reset control is required, the internal power-on reset can be used by tying the RESET

pin to VL (see Section 4.6).

Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-

es the capacitors for both the positive and negative high-voltage supplies.

Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to de-

termine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpo-

lation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference,

VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is

applied to the output amplifiers.

After this power-up state sequence is complete, normal operation begins and analog output is generated.

If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RE-

SET being set high to the analog audio output from AOUTx is less than 50 ms.

See Figure 9 for a diagram of the device’s states and transition conditions.

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DS803PP1

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