CS4353(2009) 데이터 시트보기 (PDF) - Cirrus Logic
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CS4353 Datasheet PDF : 26 Pages
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CS4353
4.6 De-emphasis Control
The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs.
The de-emphasis error will increase for sample rates other than 44.1 kHz.
When the DEM pin is connected to VL, the 44.1 kHz de-emphasis filter is activated. When the DEM pin is
connected to GND, the de-emphasis filter is turned off.
Gain
dB
T1=50 µs
0dB
-10dB
T2 = 15 µs
Note:
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 7. De-emphasis Curve, Fs = 44.1 kHz
De-emphasis is only available in Single-Speed Mode.
4.7 Internal Power-on Reset
The CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be
connected to VL during power-up and power-down sequences if the external reset function is not needed.
This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s
digital circuitry when the supply reaches defined thresholds (see “Internal Power-on Reset Threshold Volt-
ages” on page 10). No external clocks are required for the POR circuit to function.
VCP
DGND
RESET
(external)
Power-On Reset
Circuit
reset
(internal)
Figure 8. Internal Power-on Reset Circuit
When power is first applied, the POR circuit monitors the VCP supply voltage to determine when it reaches
a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the
digital circuitry. Once the VCP supply reaches the secondary threshold, Von2, the POR circuit releases the
internal reset.
Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-
neously with VCP.
When power is removed and the VCP voltage reaches a defined threshold, Voff, the POR circuit asserts the
internal reset low, resetting all of the digital circuitry.
16
DS803F1
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