C8051F521-C-IM 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F521-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

14.1.1. Internal Oscillator Suspend Mode

When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-

tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped

until one of the following events occur:

 Port 0 Match Event.

 Port 1 Match Event.

 Comparator 0 enabled and output is logic 0.

When one of the internal oscillator awakening events occur, the internal oscillator, CIP-51, and affected

peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU

resumes execution at the instruction following the write to SUSPEND.

Note: Please refer to Section “20.7. Internal Oscillator Suspend Mode” on page 212 for a note about suspend mode

in older silicon revisions.

136

Rev. 1.4

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