CS42438-DMZR 데이터 시트보기 (PDF) - Cirrus Logic

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CS42438-DMZR

108 dB, 192 kHz 6-in, 8-out TDM CODEC

Cirrus Logic 

15 REVISION HISTORY

Revision

Date

A1

July 2004

A2

October 2004

PP1

January 2005

PP2

February 2005

Changes

Initial Release

Corrected I²C Address in section 5.7.2 on page 37.

Corrected Chip I.D. in section 7.2.1 on page 42.

Initial Preliminary Product (PP) Release subject to legal notice below.

Added pin numbers to “Typical Connection Diagram (Software Mode)” on

page 10 and “Typical Connection Diagram (Hardware Mode)” on page 11.

Changed ADC Double-Speed Mode parameters. See Note 2 on page 12 and

Note 18 on page 21.

Added ADC3 MUX Interchannel Isolation characteristic in section “Character-

istics and Specifications” beginning on page 12.

Changed ADC Passband Ripple maximum specifications for SSM, DSM &

QSM in section “Characteristics and Specifications” beginning on page 12.

Changed DAC Frequency Response specifications for SSM, DSM & QSM in

section “Characteristics and Specifications” beginning on page 12.

Removed ADC Quad-Speed Mode feature. See Note 19 on page 21.

Added section “De-Emphasis Filter” on page 32.

Corrected section “TDM” on page 33.

Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB

to -64 dB) in register “AINx Volume Control (AINx_VOL[7:0])” on page 49.

Removed the register “Status Control (address 18h)”. See “CLOCK ERROR

(CLK Error)” on page 50 and “ADC Overflow (ADCX_OVFL)” on page 50 for

the Active Mode setting.

Corrected Figures 21-23.

Added section “Ordering Information” on page 62.

Table 10. Revision History

DS646PP2

63

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