CS42438-DMZR(2006) 데이터 시트보기 (PDF) - Cirrus Logic
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CS42438-DMZR Datasheet PDF : 62 Pages
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CS42438
No Power
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Power-Down (Power Applied)
1. VQ = 0 V.
2. Aout = Hi-Z.
3. No audio signal generated.
4. Control Port Registers reset
to default.
RST = Low? Yes
No
Control Port
Accessed
No
Control Port
Yes
Access Detected?
Hardware Mode
H/W pins setup to
desired settings.
No Valid MCLK
Applied?
Yes
Software Mode
Registers setup to
desired settings.
No
Valid MCLK
Applied?
Yes
PDN bit = '1'b? Yes
No
Power-Down
1. VQ discharge to 0 V.
2. Aout bias = Hi-Z.
3. No audio signal generated.
4. Control Port Registers retain
settings.
Power-Up
1. VQ = VA/2.
2. Aout bias = VQ.
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
No
Valid
MCLK/LRCK
Ratio?
Yes
2000 LRCK delay
RST = Low
ERROR: Power removed
Normal Operation
1. VQ = VA/2.
2. Aout bias = VA/2.
3. Audio signal generated per register settings.
PDN bit set
to '1'b
ERROR: MCLK/LRCK ratio change
ERROR: MCLK removed
Analog Output Mute
1. VQ = VA/2.
2. Aout bias = VA/2.
3. No audio signal generated.
Analog Output Freeze
1. VQ = VA/2.
2. Aout bias = VA/2 + last audio sample.
3. No audio signal generated.
Figure 11. Audio Output Initialization Flow Chart
DS646F1
31
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