CS8952T-IQ 데이터 시트보기 (PDF) - Cirrus Logic
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CS8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DESIGN CONSIDERATIONS
The CS8952T is a mixed-signal device containing
the high-speed digital and analog circuits required
to implement Fast Ethernet communication. It is
important the designer adhere to the following
guidelines and recommendations for proper and re-
liable operation of the CS8952T. These guidelines
will also benefit the design with good EMC perfor-
mance.
Twisted Pair Interface
The recommended connection of the twisted-pair
interface is shown if Figure 6. The unused cable
pairs are terminated to increase the common-mode
performance. Common-mode performance is also
improved by connecting the center taps of the RX
and TX input circuits to the DC-isolated ground
plane. The 0.01 µF capacitor C1 must provide 2KV
(1,500 Vrms for 60 seconds) of isolation to meet
802.3 requirements. If a shielded RJ45 connector is
used (recommended), the shield should be connect-
ed to chassis ground.
.
Internal Voltage Reference
A 4.99 kΩ 1% biasing resistor must be connected
between the CS8952T RES pin and ground. This
resistor biases the internal analog circuits of the
CS8952T and should be placed as close as possible
to RES pin. Connect the other end of this resistor
directly to the ground plane. Connect the adjacent
CS8952T ground pins (pins 85 and 87) to the
grounded end of the resistor forming a “shield”
around the RES connection.
CS8952
VSS 87
RES 86
VSS 85
4.99KΩ
1%
Via to
Ground
Plane
Figure 7. Biasing Resistor Connection and Layout
Clocking Schemes
The CS8952T may be clocked using one of three
possible schemes: using a 25 MHz crystal and the
CS8952
TX+ 80
81
TX-
RX+ 91
16
0.1µF
14
15
3
2
T1
TG22-3506
RX- 92
1
49.9Ω
1%
49.9Ω
1%
10
12
11
6
5
7
75Ω
51Ω
51Ω
51Ω
51Ω
75Ω 51Ω
51Ω
RJ-45
SHLD
1
2
3
4
5
6
7
8
SHLD
0.1µF
0.01µF
2KV
Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card)
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
63
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