CS5501 데이터 시트보기 (PDF) - Cirrus Logic

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CS5501

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

to ensure that logic inputs are maintained at either

VD+ ar DGND potential when SLEEP is low.

Note that battery life could be shortened if the +5 V

supply drops slowly during power-down. As the

supply drops below the battery voltage but not yet

below the logic threshold of the SLEEP pin, the

battery will be supplying the CS5501/CS5503 at

full power (typically 3 mA). Faster transitions at

SLEEP can be triggered using a resistive divider or

a simple resistor network to generate the SLEEP in-

put from the +5 V supply.

Output Loading Considerations

To maximize performance of the CS5501/ CS5503,

the output drive currents from the digital output

lines should be minimized.

Schematic & Layout

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