CS53L32A 데이터 시트보기 (PDF) - Cirrus Logic

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CS53L32A

Low Voltage, Stereo A/D Converter

Cirrus Logic 

CS53L32A

LRCK

SCLK

SDATA

LRCK

SCLK

SDATA

Left Channel

Right Channel

MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB

Left Justified, up to 24-Bit Data. Data Valid on Rising

Edge of SCLK.

Figure 19. CS53L32A Control Port Mode - Serial Audio Format 1

Left Channel

Right Channel

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

3R2 ciglohcktsJustified, 16-Bit Data. Data Valid on Rising Edge of

SCLK. SCLK Must Have at Least 32 Cycles per LRCK

Period.

Figure 20. CS53L32A Control Port Mode - Serial Audio Format 3

LRCK

SCLK

SDATA 0

Left Channel

Right Channel

23 22 21 20 19 18

765 43210

23 22 21 20 19 18

76543210

Right Justified, 24-Bit Data. Data Valid on Rising Edge of

32 clocks

SCLK. SCLK Must Have at Least 48 Cycles per LRCK

Period.

Figure 21. CS53L32A Control Port Mode - Serial Audio Format 4

DS513F1

35

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