ST72F324J2TARS 데이터 시트보기 (PDF) - STMicroelectronics

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ST72F324J2TARS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

10.1.9 Control register (WDGCR)

WDGCR

7

6

5

4

WDGA

R/W

3

T[6:0]

R/W

ST72324xx-Auto

Reset value: 0111 1111 (7Fh)

2

1

0

Table 35. WDGCR register description

Bit Name

Function

Activation bit

duct(s) 7 WDGA

This bit is set by software and only cleared by hardware after a reset. When

WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

ro 7-bit counter (MSB to LSB)

lete P 6:0 T[6:0]

These bits contain the value of the Watchdog counter, which is decremented every

16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh

(T6 is cleared).

bso Table 36. Watchdog timer register map and reset values

O Address (Hex.) Register label 7

6

5

4

3

2

1

0

t(s) - 002Ah

WDGCR

WDGA T6 T5 T4 T3 T2 T1 T0

reset value

0

1

1

1

1

1

1

1

Obsolete Produc 10.2

Main clock controller with real-time clock and beeper

(MCC/RTC)

The main clock controller consists of three different functions:

● a programmable CPU clock prescaler

● a clock-out signal to supply external devices

● a real-time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1

Programmable CPU clock prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal

peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 53

for more details).

The prescaler selects the fCPU main clock frequency and is controlled by three bits in the

MCCSR register: CP[1:0] and SMS.

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Doc ID 13841 Rev 1

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