ST72324xx-Auto
Figure 10. Clock, reset and supply block diagram
Supply, reset and clock management
OSC2
OSC1
Multi-
oscillator
(MO)
fOSC PLL
(option)
fOSC2
System Integrity Management
Main Clock
Controller
fCPU
with Real-time
Clock (MCC/RTC)
RESET
Reset Sequence
Manager
(RSM)
AVD Interrupt Request
SICSR
0
AVD AVD LVD
IE F RF
0
0
0
WDG
RF
Watchdog
Timer (WDG)
t(s) Low Voltage
c VSS
Detector
u VDD
(LVD)
rod Auxiliary Voltage
P Detector
te (AVD)
- Obsole 6.3
Obsolete Product(s) Caution:
Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:
● an external source
● 4 crystal or ceramic resonator oscillators
● an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 9. Refer to the Electrical characteristics section for more details.
The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an
unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.
6.3.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
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