ICS853111AV-01LFT 데이터 시트보기 (PDF) - Integrated Device Technology

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ICS853111AV-01LFT

LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER

Integrated Device Technology 

ICS853111-01

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER

LVPECL CLOCK INPUT INTERFACE

The PCLK /nPCLK accepts LVPECL, CML, SSTL and other

differential signals. Both VSWING and VOH must meet the VPP

and VCMR input requirements. Figures 3A to 3F show interface

examples for the HiPerClockS PCLK/nPCLK input driven by

the most common driver types. The input interfaces suggested

here are examples only. If the driver is from another vendor,

use their termination recommendation. Please consult with

the vendor of the driver component to confirm the driver ter-

mination requirements.

3.3V

CML

Zo = 50 Ohm

Zo = 50 Ohm

3.3V

R1

R2

50

50

3.3V

PCLK

nPCLK HiPerClockS

PCLK/nPCLK

3.3V

Zo = 50 Ohm

3.3V

R1

PCLK

100

nPCLK

Zo = 50 Ohm

HiPerClockS

CML Built-In Pullup

PCLK/nPCLK

FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY AN OPEN COLLECTOR CML DRIVER

FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A BUILT-IN PULLUP CML DRIVER

3. 3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

3. 3V

R3

R4

125

125

3.3V

PCLK

nPCLK HiPerClockS

I nput

R1

R2

84

84

3.3V

3.3V LVPECL

Zo = 50 Ohm

C1

Zo = 50 Ohm

C2

R5

100 - 200

R6

100 - 200

R1 R2

50 50

3.3V

PCLK

VBB

nPCLK

PC LK /nPC LK

FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A 3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A 3.3V LVPECL DRIVER WITH AC COUPLE

2.5V

SSTL

Zo = 60 Ohm

Zo = 60 Ohm

2.5V

R3

R4

120

120

3.3V

PCLK

R1

R2

120

120

nPCLK

HiPerClockS

PCLK/nPCLK

3.3V

LVDS

Zo = 50 Ohm

R5

100

Zo = 50 Ohm

C1

C2

R1 R2

1K 1K

3.3V

PCLK

VBB

nPCLK

PC L K /n PC L K

FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY AN SSTL DRIVER

FIGURE 3F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A 3.3V LVDS DRIVER

853111AV-01

8

REV. A NOVEMBER 14, 2007

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