R5F10367DSP-X0 데이터 시트보기 (PDF) - Renesas Electronics

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R5F10367DSP-X0

RENESAS MCU True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

Renesas Electronics 

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: TA = −40 to +105°C)

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (3/3)

(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode Unit

MIN.

MAX.

SIp setup time (to SCKp↓) tSIK1

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

88

ns

Note

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

88

ns

Cb = 30 pF, Rb = 2.7 kΩ

2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

220

ns

Cb = 30 pF, Rb = 5.5 kΩ

SIp hold time

tKSI1

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

38

ns

(from SCKp↓) Note

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

38

ns

Cb = 30 pF, Rb = 2.7 kΩ

2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

38

ns

Cb = 30 pF, Rb = 5.5 kΩ

Delay time from SCKp↑ to tKSO1

SOp output Note

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

50

ns

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

50

ns

2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 kΩ

50

ns

Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Cautions 1.

2.

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode

for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode

register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

CSI01 and CSI11 cannot communicate at different potential.

Remarks 1.

2.

Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)

load capacitance, Vb [V]: Communication line voltage

p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)

CSI mode connection diagram (during communication at different potential)

<Master>

SCKp

RL78

microcontroller

SIp

SOp

Vb

Rb

Vb

Rb

SCK

SO User's device

SI

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 87 of 106

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