R5F10367ASP-W0 데이터 시트보기 (PDF) - Renesas Electronics
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R5F10367ASP-W0 Datasheet PDF : 110 Pages
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RL78/G12
2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)
<R> (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed main) Unit
Mode
MIN.
MAX.
MIN.
MAX.
SCKp cycle time Note4 tKCY2
4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK
8/fMCK
−
ns
fMCK ≤ 20 MHz
6/fMCK
6/fMCK
ns
2.7 V ≤ VDD ≤ 5.5 V 16 MHz < fMCK
8/fMCK
−
ns
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
ns
2.4 V ≤ VDD ≤ 5.5 V
6/fMCK
6/fMCK
ns
and 500
and 500
1.8 V ≤ VDD ≤ 5.5 V
SCKp high-/low-level tKH2,
width
tKL2
SIp setup time
tSIK2
(to SCKp↑) Note 1
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
2.4 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
2.4 V ≤ VDD ≤ 5.5 V
−
6/fMCK
ns
and 750
tKCY2/2−7
tKCY2/2−7
ns
tKCY2/2−8
tKCY2/2−8
ns
tKCY2/2−18
tKCY2/2−18
ns
−
tKCY2/2−18
ns
1/fMCK +
1/fMCK +
ns
20
30
1/fMCK +
1/fMCK +
ns
30
30
1.8 V ≤ VDD ≤ 5.5 V
−
1/fMCK +
ns
30
SIp hold time
(from SCKp↑) Note 2
Delay time from
SCKp↓ to
SOp output Note 3
tKSI2
tKSO2
C = 30 pF Note4
1/fMCK +
1/fMCK +
ns
31
31
2.7 V ≤ VDD ≤ 5.5 V
2/fMCK +
44
2/fMCK +
ns
110
2.4 V ≤ VDD ≤ 5.5 V
2/fMCK +
75
2/fMCK +
ns
110
1.8 V ≤ VDD ≤ 5.5 V
−
2/fMCK +
ns
110
Notes 1.
2.
3.
4.
5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output lines.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 34 of 106
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