LFSC3GA25E-5F256I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFSC3GA25E-5F256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeSC/M Family Data Sheet

PCI Clamp

A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned

“ON” or “OFF” on each pin independently. The PCI clamp is used when implementing a 3.3V PCI interface. The PCI

Specification, Revision 2.2 requires the use of clamping diodes for 3.3V operation. For more information on the PCI

interface, please refer to the PCI Specification, Revision 2.2.

Programmable Slew Rate Control

All output and bidirectional buffers have an optional programmable output slew rate control that can be configured

for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows

designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling

edges.

Programmable Termination

Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both.

The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and

hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete compo-

nents required on the circuit board. The termination schemes can be split into two categories single-ended and differ-

ential.

Single Ended Termination

Single Ended Outputs: The SC devices support a number of different terminations for single ended outputs:

• Series

• Parallel to VCCIO or GND

• Parallel to VCCIO/2

• Parallel to VCCIO/2 combined with series

Figure 2-27 shows the single ended output schemes that are supported. The nominal values of the termination resis-

tors are shown in Table 2-10.

2-29

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