PSD853F2A-20UT 데이터 시트보기 (PDF) - STMicroelectronics
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PSD853F2A-20UT Datasheet PDF : 128 Pages
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I/O ports
PSD8XXFX
16.21
Port C – functionality and structure
Port C can be configured to perform one or more of the following functions (see Figure 28):
● MCU I/O mode
● CPLD Output – McellBC7-McellBC0 outputs can be connected to port B or port C.
● CPLD input – via the input macrocells (IMC)
● Address In – Additional high address inputs using the input macrocells (IMC).
● In-system programming (ISP) – JTAG port can be enabled for programming/erase of
the PSD device (see Section 19: Programming in-circuit using the JTAG serial interface
for more information on JTAG programming).
● Open Drain – port C pins can be configured in Open Drain mode
Port C does not support Address Out mode, and therefore no Control register is required.
Pin PC7 may be configured as the DBE input in certain MCU bus interfaces.
Figure 28. Port C structure
DATA OUT
REG.
DQ
WR
MCELLBC[ 7:0]
READ MUX
P
D
B
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT
DATA OUT
1
SPECIAL FUNCTION
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
ENABLE OUT
INPUT
MACROCELL
SPECIAL FUNCTION
PORT C PIN
CONFIGURATION
BIT
AI02888B
16.22
Port D – functionality and structure
Port D has three I/O pins. See Figure 29 and Figure 30. This port does not support Address
Out mode, and therefore no Control register is required. port D can be configured to perform
one or more of the following functions:
● MCU I/O mode
● CPLD Output – External Chip Select (ECS0-ECS2)
● CPLD input – direct input to the CPLD, no input macrocells (IMC)
● Slew rate – pins can be set up for fast slew rate
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Doc ID 7833 Rev 7
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