LTC1569-6_1 데이터 시트보기 (PDF) - Linear Technology

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LTC1569-6_1

Linear Phase, DC Accurate, Low Power, 10th Order Lowpass Filter

Linear Technology 

LTC1569-6

TYPICAL PERFOR A CE CHARACTERISTICS

THD vs Input Frequency

–60

–65

–70

VS = 5V

PIN 3 = 2V

–75

–80

–85

–90

0

VIN = 1.5VP-P

fCUTOFF = 32kHz

IN+ TO OUT

5 10 15 20 25 30

INPUT FREQUENCY (kHz)

1569-6 G01

THD vs Input Voltage

–50

–55

–60

VS = 3V

PIN 3 = 1.11V

VS = 5V

–65

PIN 3 = 2V

–70

–75

–80

–85

–90

0

fIN = 3kHz

fCUTOFF = 32kHz

IN+ TO OUT

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

INPUT VOLTAGE (VP-P)

1569-6 G02

PIN FUNCTIONS

IN +/IN – (Pins 1, 2): Signals can be applied to either or

both input pins. The DC gain from IN + (Pin 1) to OUT

(Pin␣ 8) is 1.0, and the DC gain from Pin 2 to Pin 8 is –1. The

input range, input resistance and output range are de-

scribed in the Applications Information section. Input

voltages which exceed the power supply voltages should

be avoided. Transients will not cause latchup if the current

into/out of the input pins is limited to 20mA.

GND (Pin 3): The GND pin is the reference voltage for the

filter and should be externally biased to 2V (1.11V) to

maximize the dynamic range of the filter in applications

using a single 5V (3V) supply. For single supply operation,

the GND pin should be bypassed with a quality 1µF

ceramic capacitor to V – (Pin 4). The impedance of the

circuit biasing the GND pin should be less than 2kΩ as the

GND pin generates a small amount of AC and DC current.

For dual supply operation, connect Pin␣ 3 to a high quality

DC ground. A ground plane should be used. A poor ground

will increase DC offset, clock feedthrough, noise and

distortion.

V –/V + (Pins 4, 7): For 3V, 5V and ±5V applications a

quality 1µF ceramic bypass capacitor is required from V +

(Pin 7) to V – (Pin 4) to provide the transient energy for the

internal clock drivers. The bypass should be as close as

possible to the IC. In dual supply applications (Pin 3 is

grounded), an additional 0.1µF bypass from V + (Pin 7) to

GND (Pin 3) and V – (Pin 4) to GND (Pin 3) is recom-

mended.

The maximum voltage difference between GND (Pin 3) and

V + (Pin 7) should not exceed 5.5V.

DIV/CLK (Pin 5): DIV/CLK serves two functions. When the

internal oscillator is enabled, DIV/CLK can be used to

engage an internal divider. The internal divider is set to 1:1

when DIV/CLK is shorted to V – (Pin 4). The internal divider

is set to 4:1 when DIV/CLK is allowed to float (a 100pF

bypass to V – is recommended). The internal divider is set

to 16:1 when DIV/CLK is shorted to V + (Pin 7). In the

divide-by-4 and divide-by-16 modes the power supply

current is reduced by as much as 40%.

When the internal oscillator is disabled (RX shorted

to V –) DIV/CLK becomes an input pin for applying an

external clock signal. For proper filter operation, the clock

waveform should be a squarewave with a duty cycle as

close as possible to 50% and CMOS voltages levels (see

Electrical Characteristics section for voltage levels). DIV/

CLK pin voltages which exceed the power supply voltages

should be avoided. Transients will not cause latchup if the

fault current into/out of the DIV/CLK pin is limited to 40mA.

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