V96SSC-33LP 데이터 시트보기 (PDF) - QuickLogic Corporation

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V96SSC-33LP

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

V96SSC

Table 12: Timing Relationships for Internal Register Read/Write

33 MHz

#

Sym-

bol

Description

Notes Min Max Units

1 tADO CLK2 to Data Output driving delay

1

4 12 ns

2 tADV CLK2+ADS to internal register data valid, read access time 1

49 ns

3 tADH Data hold after CLK2

1

3

ns

4 tPD IO asynchronous chip-select output delay

2

19 ns

5 tOC IO synchronous strobe output delay from CLK2

3

18 ns

6 tRZL READY float to driving low from CLK2

3 12 ns

7 tRLH READY low to high delay from CLK2

11 ns

8 tRHZ READY high to float delay from CLK2

12 ns

9 tRFV REFRESH (synchronous) output delay

14 ns

Notes:

1. For V96SSC internal register read.

2. Delays are measured from address valid and ALE asserted.

3. In IOC mode, delays are measured from CLK2 when CLK is high and ADS is asserted. In OPORT mode, de-

lays are measured from CLK2 when CLK is high during Td cycle.

Figure 7: Memory Timing Waveforms

CLK2

CLK

A31,A[26:23]

AD[15:0]

MA[11:0]

RAS

CAS

LE

WE

ADDRESS VALID

ADDR

tARA

ROW ADDR

tDRAH

D In

tRAH

COL

tCAV

tDCAH

tLEHL1

tLELH1

ADDRESS VALID

ADDR

DATA OUT

tCAH

ROW ADDR COL

tLELH2

18

V96SSC Data Sheet Rev 2.3

Copyright © 1997, V3 Semiconductor Inc.

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