M45PE10-VMN6P 데이터 시트보기 (PDF) - Numonyx -> Micron
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M45PE10-VMN6P
Numonyx -> Micron
M45PE10-VMN6P Datasheet PDF : 47 Pages
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M45PE10
DC and AC parameters
Table 12. AC characteristics (25 MHz operation)
Test conditions specified in Table 8 and Table 9
Symbol Alt.
Parameter
Min.
Typ.
Max. Unit
Clock frequency for the following
fC
fC instructions: FAST_READ, PW, PP, PE, D.C.
SE, DP, RDP, WREN, WRDI, RDSR
25
MHz
fR
tCH(1)
tCL(1)
Clock frequency for Read instructions
tCLH Clock High time
tCLL Clock Low time
Clock slew rate (2) (peak to peak)
D.C.
18
18
0.03
20
MHz
ns
ns
V/ns
tSLCH tCSS S active setup time (relative to C)
10
tCHSL
S not active hold time (relative to C)
10
tDVCH tDSU Data in setup time
5
tCHDX tDH Data in hold time
5
tCHSH
S active hold time (relative to C)
10
tSHCH
S not active setup time (relative to C)
10
tSHSL tCSH S deselect time
200
tSHQZ(2) tDIS Output disable time
tCLQV
tV Clock Low to Output valid
tCLQX tHO Output hold time
0
tRLRH(2) tRST Reset pulse width
10
tRHSL tREC Reset recovery time
tSHRH
Chip should have been deselected
before Reset is de-asserted
10
ns
ns
ns
ns
ns
ns
ns
15
ns
15
ns
ns
µs
3
µs
ns
tWHSL
tSHWL
tDP(2)
tRDP(2)
tPW(3)
Write protect setup time
Write protect hold time
S to deep power-down
S High to standby power mode
Page write cycle time (256 bytes)
Page write cycle time (n bytes)
50
ns
100
ns
3
µs
30
µs
11
10.2+
25
ms
n*0.8/256
tPP(3)
Page program cycle time (256 bytes)
Page program cycle time (n bytes)
1.2
0.4+
5
ms
n*0.8/256
tPE
Page erase cycle time
tSE
Sector erase cycle time
10
20
ms
1
5
s
1. tCH + tCL must be greater than or equal to 1/ fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one
sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
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