CS61884-IB 데이터 시트보기 (PDF) - Cirrus Logic
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CS61884-IB Datasheet PDF : 71 Pages
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CS61884
1
Test-Logic-Reset
0
0
Run-Test/Idle 1
Select-DR-Scan
0
1 Capture-DR
0
S hift-D R
1
Exit1-DR
0
Pause-DR
1
0
Exit2-DR
1
Update-DR
1
0
1
0
1
0
Select- IR-Scan 1
0
1 Capture- IR
0
Shift- IR
0
1
Exit1- IR
1
0
Pause- IR
0
1
0
Exit2- IR
1
Update- I R
1
0
Figure 16. TAP Controller State Diagram
16.1.4 Select-DR-Scan
16.1.8 Pause-DR
This is a temporary controller state.
16.1.5 Capture-DR
In this state, the Boundary Scan Register captures
input pin data if the current instruction is EXTEST
or SAMPLE/PRELOAD.
16.1.6 Shift-DR
In this controller state, the active test data register
connected between TDI and TDO, as determined
by the current instruction, shifts data out on TDO
on each rising edge of TCK.
16.1.7 Exit1-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the current
test data register.
16.1.9 Exit2-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.10 Update-DR
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the TAP
controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel
output of this register from the shift-register path
on the falling edge of TCK. The data held at the
latched parallel output changes only in this state.
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DS485F1
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