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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

CS44L10 데이터 시트보기 (PDF) - Cirrus Logic

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CS44L10
Cirrus-Logic
Cirrus Logic 
CS44L10 Datasheet PDF : 34 Pages
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CS44L10
TBCF
Fs
00
01
10
11
LRCK in Single Speed Mode (DBS=0)
48 kHz
24 kHz
12 kHz
8 kHz
2 kHz
1 kHz
0.5 kHz
0.33 kHz
4 kHz
2 kHz
1 kHz
0.67 kHz
7 kHz
3.5 kHz
1.75 kHz
1.17 kHz
Reserved
Reserved
Reserved
Reserved
Table 7. Treble Boost Corner Frequencies in Single Speed Mode
4.5.3 TONE CONTROL MODE (TC)
Default = 00
00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user-defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to 00. Alternately, one of three pre-defined settings may be used (these settings
are a function of LRCK - refer to tables 5, 6, and 7).
Note: Treble boost is not available in Double Speed Mode.
4.5.4 TONE CONTROL ENABLE (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
4.5.5 PEAK SIGNAL LIMITER ENABLE (LIM_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44L10 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate
register.
Once the signal has dropped below the clipping level, the attenuation is decreased back to the user se-
lected level followed by the Bass Boost being increased back to the user selected level. The release rate
is determined by the Limiter Release Rate register.
Note: The A=B bit should be set to 1for optimal limiter performance.
DS541PP1
17

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