CS43L41 데이터 시트보기 (PDF) - Cirrus Logic

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CS43L41

Low Power 24-Bit, 96 kHz DAC with Volume Control

Cirrus Logic 

CS43L41

4. REGISTER BIT DESCRIPTION

4.1 MASTER CLOCK DIVIDE ENABLE

MCLK Control Register (address 00h)

7

Reserved

6

Reserved

5

Reserved

4

Reserved

Access:

R/W in I2C and write only in SPI.

3

Reserved

2

Reserved

1

MCLKDIV

0

Reserved

Default:

0 - Disabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

Note: This feature is present on revision C and newer devices. For backward compatibility with pre-

vious revision devices, this bit defaults to zero.

MCLKDIV

0

Disabled

1

Enabled

MODE

Table 1. Master Clock Divide Enable

4.2 AUTO-MUTE

Mode Control Register (address 01h)

7

AMUTE

6

DIF2

5

DIF1

4

DIF0

3

DEM1

2

DEM0

1

POR

0

PDN

Access:

R/W in I2C and write only in SPI.

Default:

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and mut-

ing is done independently for each channel. The quiescent voltage on the output will be retained and

the Mute Control pin will go active during the mute period. The muting function is effected, similar to

volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.

AMUTE

0

1

Disabled

Enabled

MODE

Table 2. Auto-Mute Enable

DS473PP1

15

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