74LVQ125SC 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74LVQ125SC Datasheet PDF : 5 Pages
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February 1992
Revised June 2001
74LVQ125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVQ125 contains four independent non-inverting buff-
ers with 3-STATE outputs.
Features
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
74LVQ125SC
Package Number
Package Description
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVQ125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An, Bn
On
Description
Inputs
Outputs
Truth Table
Inputs
An
Bn
L
L
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
Output
On
L
H
Z
© 2001 Fairchild Semiconductor Corporation DS011349
www.fairchildsemi.com
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