ST7FMC2N6B6(2004) 데이터 시트보기 (PDF) - STMicroelectronics

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ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

REPETITION COUNTER REGISTER (MREP)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

REP7 REP6 REP5 REP4 REP3 REP2 REP1 REP0

Bits 7:0 = REP[7:0] Repetition counter value (N).

This register allows the user to set-up the update

rate of the PWM counter compare register (i.e. pe-

riodic transfers from preload to active registers),

as well as the PWM Update interrupt generation

rate, if these interrupts are enabled.

Each time the MREP related Down-Counter

reaches zero, the Compare registers are updated,

a U interrupt is generated and it re-starts counting

from the MREP value.

After a microcontroller reset, setting the CKE bit in

the MCRA register (i.e. enabling the clock for the

MTC peripheral) forces the transfer from the

MREP preload register to its active register and

generates a U interrupt. During run-time (while

CKE bit = 1) a new value entered in the MREP

preload register is taken into account after a U

event.

As shown in Figure 120, (N+1) value corresponds

to:

– The number of PWM periods in edge-aligned

mode

– The number of half PWM periods in center-

aligned mode.

–

COMPARE PHASE W PRELOAD REGISTER

HIGH (MCPWH)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

CPWH CPWH CPWH CPWH CPWH CPWH CPWH CPWH

7

6

5

4

3

2

1

0

Bits 7:0 = CPWH[7:0] Most Significant Byte of

phase W preload value

COMPARE PHASE W PRELOAD REGISTER

LOW (MCPWL)

Read/Write (except bits 2:0)

Reset Value: 0000 0000 (00h)

7

0

CPWL CPWL CPWL CPWL CPWL

7

6

5

4

3

-

-

-

Bits 7:5 = CPWL[7:3] Low bits of phase W preload

value.

Bits 2:0 = Reserved.

COMPARE PHASE V PRELOAD REGISTER

HIGH (MCPVH)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

CPVH7 CPVH6 CPVH5 CPVH4 CPVH3 CPVH2 CPVH1 CPVH0

Bit 7:0 = CPVH[7:0] Most Significant Byte of

phase V preload value

COMPARE PHASE V PRELOAD REGISTER

LOW (MCPVL)

Read/Write (except bits 2:0)

Reset Value: 0000 0000 (00h)

7

0

CPVL7 CPVL6 CPVL5 CPVL4 CPVL3 -

-

-

Bits 7:5 = CPVL[7:3] Low bits of phase V preload

value.

Bits 2:0 = Reserved.

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