ST7FMC2N6B6(2004) 데이터 시트보기 (PDF) - STMicroelectronics

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ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.11 Speed Sensor Mode

This mode is entered whenever the Tacho Edge

Selection bits in the MPAR register are not both re-

set (TES[1:0] = 10, 01, 11). The corresponding

block diagram is shown in Figure 86.

Either Incremental Encoder or Tachogenerator-

type speed sensor can be selected with the IS[1:0]

bits in the MPHST register.

9.6.6.12 Tachogenerator Mode (IS[1:0] = 00, 01

or 10)

Any of the MCIx input pins can be used as a tacho-

generator input, with a digital signal (externally

amplified for instance); the two remaining pins can

be used as standard I/O ports.

A digital multiplexer connects the chosen MCIx in-

put to an edge detection block. Input selection is

done with the IS[1:0] bits in the MPHST register.

An edge selection block is used to select one of

three ways to trigger capture events: rising edge,

falling edge or both rising and falling edge sensi-

tive; set-up is done with the TES[1:0] bits (keeping

in mind that TES[1:0] = 00 configuration is re-

served for Position Sensor / Sensorless Modes).

Having only one edge selected eliminates any in-

coming signal dissymmetry, which may due to

pole-to-pole magnet dissymmetry or from a com-

parator threshold with low level signals.

Figure 87 presents the signals generated internal-

ly with different tacho input and TES bit settings.

Note on Hall Sensors: This configuration is also

suitable for motors using 3 hall sensors for position

detection and not driven in six-step mode (refer to

“Speed Measurement Mode” on page 176).

Note on initializing the Input Stage: As the

IS[1:0] bits in the MPHST register are preload bits

(new values taken into account at C event), the in-

itialization value of the IS[1:0] bits has to be en-

tered in Direct Access mode. This is done by set-

ting the DAC bit in the MCRA register during the

speed sensor input initialization routine.

Figure 86. Input Stage in Speed Sensor Mode (TES[1:0] bits = 01, 10, 11)

Input Block

Input Comparator Block

Event Detection

In1 Incremental

Encoder

In2 interface

Encoder

Clock

Clk

D Direction

MPHST Register

Inputn Sel

IS[1:0]

EDIR bit

MCRC Register

Tacho§ or MCIA

Encoder

00

Tacho§ or MCIB

01

Encoder

MPAR Register

TES[1:0]

or or

Tacho

Capture

Tacho§ or MCIC

10

Free I/O

§ = According to IS[1:0] bits setting

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