CS8414-CS 데이터 시트보기 (PDF) - Cirrus Logic
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CS8414-CS Datasheet PDF : 38 Pages
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CS8413 CS8414
Multifunction Pins
There are seven multifunction pins which contain
either error and received frequency information, or
channel status information, selectable by SEL.
Error and Frequency Reporting
When SEL is low, error and received frequency in-
formation are selected. The error information is en-
coded on pins E2, E1, and E0, and is decoded as
shown in Table 5. When an error occurs, the corre-
sponding error code is latched. Clearing is then ac-
complished by bringing SEL high for more than
eight MCK cycles. The errors have a priority asso-
ciated with their error code, with validity having
the lowest priority and no lock having the highest
priority. Since only one code can be displayed, the
error with the highest priority that occurred since
the last clearing will be selected.
E2
E1
E0
Error
0
0
0
No Error
0
0
1
Validity Bit High
0
1
0
Reserved
0
1
1
Slipped Sample
1
0
0
CRC Error (PRO only)
1
0
1
Parity Error
1
1
0
Bi-phase Coding Error
1
1
1
No Lock
Table 5. Error Decoding
The validity flag indicates that the validity bit for a
previous sample was high since the last clearing of
the error codes. The slipped sample error can only
occur when FSYNC and SCK of the audio serial
port are inputs. In this case, if FSYNC is asynchro-
nous to the received data rate, periodically a stereo
sample will be dropped or reread depending on
whether the read rate is slower or faster than the re-
ceived data rate. When this occurs, the slipped sam-
ple error code will appear on the ‘E’ pins. The CRC
error is updated at the beginning of a channel status
block, and is only valid when the professional for-
mat of channel status data is received. This error is
indicated when the CS8414 calculated CRC value
does not match the CRC byte of the channel status
block or when a block boundary changes (as in re-
moving samples while editing). The parity error oc-
curs when the incoming sub-frame does not have
even parity as specified by the standards. The bi-
phase coding error indicates a biphase coding vio-
lation occurred. The no lock error indicates that the
PLL is not locked onto the incoming data stream.
The received frequency information is encoded on
pins F2, F1, and F0, and is decoded as shown in Ta-
ble 6. The on-chip frequency comparator compares
the received clock frequency to an externally sup-
plied 6.144 MHz clock which is input on the FCK
pin. The ‘F’ pins are updated three times during a
channel status block including prior to the rising
edge of CBL. CBL may be used to externally latch
the ‘F’ pins. The clock on FCK must be valid for
two thirds of a block for the ‘F’ pins to be accurate.
The ‘F’ pins are invalid when the PLL is out of
lock.
F2
F1
F0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Sample Frequency
Out of Range
reserved
reserved
96 kHz ±4%
88.2 kHz ±4%
48 kHz ±4%
44.1 kHz ±4%
32 kHz ±4%
Table 6. Sample Frequency Decoding
Channel Status Reporting
When SEL is high, channel status is displayed on
C0, and Ca-Ce for the channel selected by CS12. If
CS12 is low, channel status for sub-frame 1 is dis-
played, and if CS12 is high, channel status for sub-
frame 2 is displayed. The contents of Ca-Ce depend
24
DS240F1
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