PSD815G3V-C-90UI 데이터 시트보기 (PDF) - STMicroelectronics

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PSD815G3V-C-90UI

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD835G2

Microcontroller Interface – PSD835G2 AC/DC Parameters

(3.0 V to 3.6 V Versions)

Power Down Timing (3.0 V to 3.6 V Versions)

Symbol

Parameter

t LVDV

ALE Access Time from

Power Down

t CLWH

Maximum Delay from APD Enable

to Internal PDN Valid Signal

NOTE: 1. tCLCL is the CLKIN clock period.

Conditions

Using CLKIN Input

Vstbyon Timing (3.0 V to 3.6 V Versions)

Symbol

Parameter

t BVBH

Vstby Detection to Vstbyon Output

High

t BXBL

Vstby Off Detection to Vstbyon

Output Low

NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

Conditions

(Note 1)

(Note 1)

Reset Pin Timing (3.0 V to 3.6 V Versions)

Symbol

Parameter

t NLNH

t OPR

t NLNH-PO

t NLNH-A

Warm RESET Active Low Time (Note 1)

RESET High to Operational Device

Power On Reset Active Low Time

Warm RESETActive Low Time

(Note 2)

NOTE: 1. RESET will not abort Flash programming/erase cycles.

2. RESET will abort Flash programming or erase cycle.

Conditions

PSD8XX Family

-90

-12

Min Max Min Max Unit

128

135 ns

15 * tCLCL (µs) (Note 1)

µs

Min

Typ

Max Unit

20

µs

20

µs

Min

Typ

Max Unit

300

ns

300

ns

1

ms

25

µs

93

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