PSD4135F-C-70UI 데이터 시트보기 (PDF) - STMicroelectronics
부품명
상세내역
제조사
PSD4135F-C-70UI Datasheet PDF : 110 Pages
| |||
PSD8XX Family
PSD835G2
PSD835G2 DC Characteristics (3.0 V to 3.6 V Versions) Advance Information
Symbol
Parameter
VCC
VIH
VIL
VIH1
VIL1
VHYS
VLKO
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
VCC Min for Flash Erase and Program
VOL
Output Low Voltage
VOH
VOH1
VSBY
ISBY
IIDLE
VDF
ISB
ILI
ILO
IO
Output High Voltage Except VSTBY On
Output High Voltage VSTBY On
SRAM Standby Voltage
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
SRAM Data Retention Voltage
Standby Supply Current
for Power Down Mode
Input Leakage Current
Output Leakage Current
Output Current
ICC (DC) Operating
(Note 5) Supply Current
PLD Only
FLASH
ICC (AC)
(Note 5)
PLD AC Base
FLASH
AC Adder
SRAM AC Adder
SRAM
Conditions
Min Typ Max Unit
All Speeds
3.0
3.6
V
3.0 V < VCC < 3.6 V
3.0 V < VCC < 3.6 V
(Note 1)
(Note 1)
.7 VCC
– .5
.8 VCC
–.5
0.3
VCC +.5
V
0.8
V
VCC +.5
V
.2 VCC –.1
V
V
1.5
2.3
V
IOL = 20 µA, VCC = 3.0 V
0.01
0.1
V
IOL = 4 mA, VCC = 3.0 V
0.15
0.45
V
IOH = –20 µA, VCC = 3.0 V
2.9
2.99
V
IOH = –1 mA, VCC = 3.0 V
2.7
2.8
V
IOH1 = 1 µA
VCC = 0 V
VSBY – 0.8
V
2.0
VCC
V
0.5
1
µA
VCC > VSBY
Only on VSTBY
– 0.1
2
0.1
µA
V
CSI >VCC –0.3 V
(Notes 2 and 3)
50
100
µA
VSS < VIN < VCC
0.45 < VIN < VCC
Refer to IOL and IOH in
the VOL and VOH row
ZPLD_TURBO = OFF,
f = 0 MHz (Note 3)
–1
±.1
1
µA
–10
±5
10
µA
0
mA
ZPLD_TURBO = ON,
f = 0 MHz
200
400
µA/PT
During FLASH
Write/Erase Only
10
25
mA
Read Only, f = 0 MHz
0
0
mA
f = 0 MHz
0
0
mA
(Note 4)
Figure 32a
1.5
2.0 mA/MHz
0.8
1.5 mA/MHz
NOTES: 1.
2.
3.
4.
5.
Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.
CSI deselected or internal PD mode is active.
PLD is in non-turbo mode and none of the inputs are switching.
Refer to Figure 31a for PLD current calculation.
IO = 0 mA.
86
Share Link: 