DATA
BUS
8
PAGE
REGISTER
8
DECODE PLD
82
4
1
1
2
1
16 OUTPUT MICRO⇔CELL FEEDBACK
FLASH MEMORY SELECTS
FLASH BOOT MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
PERIPHERAL I/O MODE SELECTS
JTAG SELECT
DIRECT MICRO⇔CELL ACCESS FROM MCU DATA BUS
CPLD
16 OUTPUT
MICRO⇔CELL
PT
82
ALLOC.
24 INPUT MICRO⇔CELL
(PORT A,B,C)
DIRECT MICRO⇔CELL INPUT TO MCU DATA BUS
24
INPUT MICRO⇔CELL & INPUT PORTS
12
PORT D AND F INPUTS
MCELLA
TO PORT A
8
MCELLB
TO PORT B
8
8
EXTERNAL CHIP SELECTS
TO PORT C OR F