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PIC16CR64T-04/SO 데이터 시트보기 (PDF) - Microchip Technology

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PIC16CR64T-04/SO
Microchip
Microchip Technology 
PIC16CR64T-04/SO Datasheet PDF : 336 Pages
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PIC16C6X
4.2.2.4 PIE1 REGISTER
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
This register contains the individual enable bits for the
peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch)
RW-0 R/W-0
U-0
bit7
U-0
R/W-0 R/W-0
SSPIE CCP1IE
bit 7-6:
bit 5-4:
bit 3:
bit 2:
bit 1:
bit 0:
Reserved: Always maintain these bits clear.
Unimplemented: Read as '0'
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30234D-page 38
© 1997 Microchip Technology Inc.

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