PCA8538UG(2014) 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA8538UG
(Rev.:2014)

Automotive 102 x 9 Chip-On-Glass LCD segment driver

NXP Semiconductors. 

NXP Semiconductors

PCA8538

Automotive 102 x 9 Chip-On-Glass LCD segment driver

15. Application information

15.1 ITO layout recommendations for ESD/EMC robustness in COG

applications

The crucial factor for gaining an EMC and ESD robust application is the quality of the

VSS1 line.

• To get an EMC/ESD robust ITO/glass layout, the RITO(VSS1) has to be kept as low as

possible.

• In the most common applications VSS1 will be connected to the pins T1, T2, A0, A1,

OSC, SA0, SA1 and IFS (in the case of using the SPI interface) by using a very wide

ITO connection

• If possible, the ITO connection of VSS1 should be made wide, for example by fanning

out the other connections

• When the display is enabled, the charge and discharge caused by display activity

affects the VSS1 line. This causes a dynamic current in the VSS1 line which means

that dynamic voltage peaks in the VSS1 line may interfere with the low voltage part of

the PCA8538. Therefore a low RITO(VSS1) is also important for an improved noise

immunity of the PCA8538 especially at high VLCD values (VLCD > 10 V).

• A low RITO(VSS1) will also improve the communication stability with the microcontroller

by reducing the effects of local ground (VSS1) bounce caused by high SDAACK

currents.

• It should be considered that VSS1 is internally connected to the IC substrate,

therefore noise on the VSS1 line will cause noise inside the IC.

Figure 59 and Figure 60 are showing the recommended ITO connections for a COG

layout according to the interface type use.

PCA8538

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 26 September 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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