PC48F4400PMVB0 데이터 시트보기 (PDF) - Numonyx -> Micron
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PC48F4400PMVB0 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For
example, an Erase Setup command must be immediately followed by the Erase Confirm
command in order to execute properly. If a different command is issued between the
setup and confirm commands, the partition is placed in read-status mode, the Status
Register signals a command sequence error, and all subsequent erase commands to
that partition are ignored until the Status Register is cleared.
The CPU can detect block erase completion by analyzing SR[7] of that partition. If an
error bit (SR[5,3,1]) was flagged, the Status Register can be cleared by issuing the
Clear Status Register command before attempting the next operation. The partition
remains in read-status mode until another command is written to its CUI. Any CUI
instruction can follow after erasing completes. The CUI can be set to read-array mode
to prevent inadvertent Status Register reads.
Datasheet
68
November 2007
Order Number: 290701-18
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