M45PE20-VMN6TP 데이터 시트보기 (PDF) - STMicroelectronics

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M45PE20-VMN6TP

2 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface

STMicroelectronics 

M45PE20

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7.)

sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set pri-

or to every Page Write (PW), Page Program (PP),

Page Erase (PE), and Sector Erase (SE) instruc-

tion.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 7. Write Enable (WREN) Instruction Sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8.)

resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

– Power-up

– Write Disable (WRDI) instruction completion

– Page Write (PW) instruction completion

– Page Program (PP) instruction completion

– Page Erase (PE) instruction completion

– Sector Erase (SE) instruction completion

Figure 8. Write Disable (WRDI) Instruction Sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

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