M25PE10-VMN6TP 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

제조사

M25PE10-VMN6TP

1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

M25PE20, M25PE10

14 Revision history

Revision history

Table 28. Document revision history

Date

Version

Changes

07-Dec-2004 0.1 Document written

21-Dec-2004

0.2

Notes 1 and 2 removed from Table 27: Ordering information scheme.

S08N silhouette corrected on page 1.

6-Oct-2005

Added <Blue>Table 21., AC characteristics (33 MHz operation).

Document status promoted to full Datasheet. An easy way to modify

data, A fast way to modify data, Page Write (PW) and Page Program

1.0 (PP) sections updated to explain optimal use of Page Write and Page

Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.

Updated <Blue>Table 27., Ordering information scheme. Added

Ecopack® information.

10-Jul-2006

25-Jan-2007

Document converted to the new ST template.

MLP package removed, SO8N package specifications updated (see

2

Section 12: Package mechanical).

Figure 5: SPI modes supported updated and Note 2 added. Timing line

of tSHQZ moved in Figure 29.

50 MHz frequency added. VFQFPN package added (see Section 12:

Package mechanical).

The sectors are further divided up into subsectors (see Table 5:

M25PE20 memory organization and Table 6: M25PE10 memory

organization). Important note on page 6 added. Figure 4: Bus master

and memory devices on the SPI bus updated and explanatory paragraph

added. VCC supply voltage and VSS ground added. Section 4.8:

Protection modes modified. Section 8: Reset added, Reset timings table

split into Table 23: Reset conditions and Table 24: Timings after a Reset

Low pulse.

At Power-up the WIP bit is reset and the Lock Registers are reset (see

Section 7: Power-up and power-down).

VIO max changed in Table 15: Absolute maximum ratings.

3

M25PE20 and M25PE10 products processed in T9HX process added to

datasheet:

– WP pin replaces TSL (T7X technology), see Section 2.7: Write Protect

(W) or Top Sector Lock (TSL)

– Read Lock Register (RDLR), Write to Lock Register (WRLR), Write

Status Register (WRSR), SubSector Erase (SSE) and Bulk Erase

(BE) instructions added for T9HX process

– subsector protection granularity removed in T9HX process, still exists

in T7X process

– Table 5: M25PE20 memory organization and Table 6: M25PE10

memory organization updated to show subsectors

– Status Register BP1, BP0 bits and SRWD bit added.

Small text changes.

59/60

Share Link: